how to define an unsigned signal in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity YourEntityName is
Port ( your_signal : out unsigned(7 downto 0));
end YourEntityName;
architecture Behavioral of YourEntityName is
begin
-- Your VHDL code here
end Behavioral;